1. Field of the Invention
The present invention relates to a semiconductor integrated circuit comprising a memory cell and a method of controlling the same. In particular, the present invention relates to a semiconductor integrated circuit having a data masking function.
2. Description of the Related Art
With the development of semiconductor manufacturing technologies, semiconductor integrated circuits have been increasing its operating speed. In particular, the operating frequencies of microcomputers and the like have been improving year after year, further increasing the difference with the operating frequencies of semiconductor memories such as a DRAM.
To reduce this difference, high-speed memories including SDRAMs (Synchronous DRAMs), DDR SDRAMS (Double Data Rate Synchronous DRAMs), and FCRAMs (Fast cycle RAMs) have been developed.
FIG. 1 shows an example of a DDR SDRAM (hereinafter, also simply referred to as SDRAM) in which data are input/output in synchronization with rising edges and falling edges of a clock signal. Parenthetically, in the drawings, those signal lines shown by thick lines each comprise a plurality of lines. Some of the circuits connected with the thick lines consist of a plurality of components.
The SDRAM comprises an input/output control unit 1, a chip control unit 2, and a plurality of memory core units 3. If the SDRAM consists of a plurality of banks, a group of the chip control unit 2 and the memory core units 3 are provided for each of the banks.
The input/output control unit 1 comprises a clock buffer 4, a command decoder 5, an address buffer 6, a DQS butter 7, a mask buffer/latch 8, an input/output buffer/register 9, serial-parallel converters 10 and 11, and a parallel-serial converter 12.
The clock buffer receives a clock signal CLK from the exterior and outputs the received signal to a predetermined circuit as an internal clock signal ICLK. The command decoder 5 receives a command signal CMD, analyzes the received command and outputs the resultant as an internal command signal ICMD. The address buffer 6 receives an address signal AD, and outputs the received signal as an internal address signal IAD. The SDRAM does not adapt an address multiplex type; therefore, the address signal A/D is supplied once in every read operation and in every write operation.
The DQS buffer 7 receives a data strobe signal DQS, and outputs the received signal as an internal data strobe signal IDQS. The mask buffer/latch 8, when an enable signal ENA is activated, accepts a data mask signal DM in synchronization with the internal data strobe signal IDQS. The mask buffer/latch 8 then outputs the accepted signal to the serial-parallel converter 10. The input/output buffer/register 9 receives an output data signal DOUT in a read operation. When the enable signal ENA is activated, the received signal is output as a data signal DQ in synchronization with the internal data strobe signal IDQS. Moreover, the input/output buffer/register 9, when the enable signal ENA is activated in a write operation, accepts a data signal DQ in synchronization with the internal data strobe signal IDQS. The accepted data is output as an input data signal DIN.
The serial-parallel converter 10 converts mask signals sequentially supplied from the mask buffer/latch 8 into a parallel form and outputs the resultant as an internal mask signal IDM. The serial-parallel converter 11 sequentially receives input data signals DN of serial form supplied from the input/output buffer/register 9. The serial-parallel converter 11 converts the received signals into a parallel form, and outputs the resultant as a write data signal WDB. The parallel-serial converter 12 converts a read data signal RDB of parallel form, supplied from a sense buffer 16 into serial forms. The parallel-serial converter 12 sequentially outputs the resultants as output data signals DOUT.
The chip control unit 2 comprises a command latch 13, a control circuit 14, a data masking circuit 15, the sense buffer 16, and a write amplifier 17.
The command latch 13 receives the internal command signal ICMD, and outputs a read control signal RD, a write control signal WR, and the like, in accordance with the received signal. The control circuit 14 receives the read control signal RD and the write control signal WR, and outputs the enable signal ENA and a plurality of timing signals. The timing signals are supplied to the sense buffer 16 and the write amplifier 17, along with row decoders 19, sense amplifiers 20, and column decoders 21 in the memory core units 3.
The data masking circuit 15 masks a predetermined bit or bits of the write data signal WDB in accordance with the internal mask signal IDM. The masked signal is output as a write data signal WDBM.
The sense buffer 16 receives a data signal DB from the memory core units 3, and outputs the received signal as the read data signal RDB in synchronization with the timing signal. The write amplifier 17 receives the write data signal WDBM, and outputs the received signal as a data signal DB in synchronization with the timing signal.
The memory core units 3 each comprise a memory cell unit 18, the row decoder 19, the sense amplifier 20, and the column decoder 21. The memory cell unit 18 includes a plurality of memory cells MC.
The row decoder 19 receives the timing signal and a predecoding signal generated from the internal address signal IAD and activates word lines WL connected with the memory cells MC. The column decoder 21 receives the timing signal and the predecoding signal generated from the internal address signal IAD and activates column switches (not shown) connected with bit lines BL. The sense amplifier 2 amplifies data transmitted from the memory cells MC through the bit lines BL in a read operation and amplifies the data signal DB supplied in a write operation.
FIG. 2 shows an example where the SDRAM described above executes a write operation between read operations. In this example, the read latency, which is a number of clocks from the reception of a read command to the output of read data, is "2". The write latency, which is a number of clocks from the reception of a write command to the reception of write data, is "0".
In the following descriptions, some abbreviations may be used such as "CLK signal" for the "clock signal CLK".
For a start, read commands RD0 and RD1 are sequentially supplied in synchronization with the CLK signal to operate the memory core units 3 (FIG. 2(a)). Read addresses not shown are supplied along with the read commands. The memory core units 3 output read data approximately one clock after the reception of the respective read commands. Subsequently, input/output circuit is operated (FIG. 2(b)). Here, the input/output circuit corresponds to the sense buffer 16, the parallel-serial converter 12, and the input/output buffer/register 9 shown in FIG. 1.
Then, read data Q00, Q01, Q10, and Q11 are sequentially output as the data signals DQ, two clocks after the reception of the respective read commands RD0 and RD1. The read data Q00 and Q01, as well as Q10 and Q11, are generated by the parallel-serial converter 12 converting the read data RDB of parallel form.
Subsequently is supplied a write command. Since the terminals to transmit those DQ signals are input/output terminals, write data DA0 and DA1 cannot be supplied until after the output of the read data Q11 for the sake of avoiding a signal conflict. Besides, with the write latency at "0", the write command WRA is supplied in synchronization with the same CLK signal as the write data DA0 (FIG. 2(c)). Though omitted of specific illustration, a write address is supplied along with the write data.
After the reception of the write command WRA, input/output circuit is operated to convert the write data DA0 and DA1 into a parallel form. The converted write data WDB are masked for a predetermined bit or bits by the data masking circuit 15, and transmitted to the memory core units 3 as write data WDBM (FIG. 2(d)). The input/output circuit here corresponds to the input/output buffer/register 9, the serial-parallel converter 11, the data masking circuit 15, and the write amplifier 17 shown in FIG. 1. The memory core units 3 operate approximately one clock after the reception of the write command WRA, writing the data to the memory cells MC (FIG. 2(e)).
Next, a read command is supplied. Here, in order to prevent the operational overlaps of the memory core units 3, the read command RD2 needs to be supplied in synchronization with the CLK signal two clocks after the reception of the write command WRA. Subsequently, the memory core units 3 and the input/output circuit make the same operation as the read operations described above (FIG. 2(f)). Then, the first read data Q20 is output after two clocks corresponding to the read latency.
As described above, the SDRAM shown in FIG. 1 transmits no data signal DQ over a period of three clocks or more when performing a read operation after a write operation. This consequently lowers the usage efficiency of the data bus for transmitting data signals DQ.
FIG. 3 shows another example of a DDR SDRAM.
This SDRAM differs from that of FIG. 1 in the circuit configuration of the chip control unit 2. That is, the SDRAM has a shift register 22 between the command latch 13 and the control circuit 14. The shift register 22 accepts the WR signal output from the command latch 13, delays the accepted signal by a predetermined number of clocks, and outputs the delayed signal to the control circuit 14 as a delayed write control signal WRD. On this account, the control circuit 14 starts operating the predetermined number of clocks after the write command is supplied. The other circuit configuration is the same as that of FIG. 1.
FIG. 4 shows an example where the SDRAM described above executes a write operation between read operations. In this example, both the read latency and the write latency are "2".
The operations corresponding to the initially-supplied read commands RD0 and RD1 are identical to as those of FIG. 2, and therefore description thereof will be omitted.
In this SDRAM, the write command WRA is supplied two clocks after the reception of the read command RD1. Since the write latency in this example is "2", the write data DA0 and DA1 are supplied two clocks after the write command WRA. That is, the write data DA0 and DA1 are supplied in synchronization with the CLK signal that comes after the output of the read data Q11 (FIG. 4(a)).
Subsequently, the write operation and read operations are executed under the same timing as that of FIG. 2.
In the SDRAM shown in FIG. 3, the write command can be supplied at earlier timing, whereas the internal operations are identical to those of FIG. 2. Therefore, as under the timing shown in FIG. 2, no data signal DQ is transmitted over a period of three clocks or more when the read operation is performed after the write operation, thereby lowering the usage efficiency of the data bus.
As seen from above, conventional SDRAMS have had a problem that random accesses including both read and write operations lower the usage efficiencies of their data buses. A drop in the usage efficiency of data bus decreases the amount of data transfer per unit time. Accordingly, it has been difficult to apply high-speed memories such as SDRAMs to graphics memories which perform frequent random accesses such as image processing.
For a further improvement of the usage efficiency of the data bus, there has been recently proposed an SDRAM having a so-called "delayed write" function, in which write data supplied corresponding to a write command is written to memory cells when the next write command is supplied.
FIG. 5 shows an example where an SDRAM having the delayed write function of this type performs write operations in between read operations. In this example, both the read latency and the write latency are "2".
The operations corresponding to the read commands RD0 and RD1 initially supplied are identical to those of FIG. 2, and therefore descriptions thereof will be omitted.
In this SDRAM, a write command WR0 is supplied two clocks after the reception of the read command RD1. Since the read latency in this example is set at "2", write data DA0 and DA1 are supplied two clock after the write command WR0. That is, the write data DA0 and DA1 are supplied in synchronization with the CLK signal that comes after the output of the read data Q11 (FIG. 5(a)).
Here, the write data DA0 and DA1 are not written to the memory cells but are held in a register (FIG. 5(b)).
Subsequently, read commands RD2, RD3, and RD4 are sequentially supplied in synchronization with the CLK signal following the write command WR0, whereby read operations are performed at the same timing as that of FIG. 2 (FIG. 5(c)). The memory core units have not performed a write operation so they can immediately perform the read operations. In the SDRAM with the delayed write function, it is consequently possible to minimize the period of not transmitting the data signal DQ, thereby improving the usage efficiency of data bus.
Moreover, the next write command WR1 is supplied two clocks after the reception of the read command RD4 (FIG. 5(d)). In synchronization with the reception of this write command WR1, the input/output circuit and the memory core units operate so that the previous write data DA0 and DA1 held in the register are written to the memory cells (FIG. 5(e)).
Then, write data DA2 and DA3 are supplied two clocks after the write command WR1. The contents of the register are rewritten to the write data DA2 and DA3 (FIG. 5(f)).
In this way, the SDRAM with the delayed write function can execute write operations on the memory cells independent of the accepting timing of write data. Therefore, it can prevent the overlap of the operations of the memory core units respectively corresponding to a write command and the read command supplied immediately after the write command. This consequently improves the usage efficiency of data bus and enhances the amount of data transfer as compared to the SDRAMs shown in FIGS. 1 and 2.
Now, the SDRAMs with the delayed write function are of recently proposed technology and have matters to be considered before commercialization.
For example, the data masking function to mask a predetermined bit or bits of write data is indispensable for graphics memories, however, it has not been specifically considered in the SDRAMs with the delayed write function. Consequently, the SDRAMs with the conventional delayed write function have not been applicable to graphics memories or the like, which require the data masking function.